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Konferenčná stáž

BE-12-71-VUB from Belgium

Basic information

Fee:	132 EUR
Deadline for nomination:	March 31, 2012

Employer information

Employer:	EASICS	Working place:	Leuven
Address:	hidden	Official responsible:	hidden
	hidden	Nearest international airport:	Brussels
Business or product:	System on chip	Nearest public transport:	Heverlee
Number of employees:		Weekly Working hours:
Canteen facilities:		Daily Working hours:

Student information

Faculty:	Computer Science, Electronics	Language:
Specialization:		Excellent English
Study level:	Middle
Previous training req.:	No
Other requirements:	demonstrated experiences in advanced C++ programing and with flex and bison, knowledge of Python and C-bindings, notions of Verilog and FPGA/ASIC hardware design
Gender:	Either

Work offered

Kind of work:		Weeks offered:	6 - 8
Software development of an ASIC/FPGA Netlist Checking Tool. The purpose of this project is to develop a software tool that extracts information from verilog netlist of a digital ASIC or FPGA design. It will be able to detect violations against bad design practices, involving clocks, reseats, memory access, etc. This tool will be written in C++ as a Linux application and will be set up as a python extension. The mail task of the project are: - Transform parse trees from a verilog parser and liberty parser into a structure that is convenient for the required manipulations. - Write a number of procedures that extract information, detect design violations or extract parts of the netlist - Write Python bindings for these procedure		Within:	January 01, 2012 - November 30, 2012
Categories:		Gross pay:	170 EUR / Weekly
- Professional		Deduction expected:
- Research & Development
- Working Environment

Accomodation

Lodging will be arranged by:	IAESTE
Estimated cost of lodging:	350 EUR / Month
Estimated cost of living incl. lodging:	650 EUR / Month

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